The present invention relates to a process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit, wherein active regions of electronic components have already been defined.
The invention relates, in particular but not solely, to electronic devices having a driver circuit and one or more power transistors integrated monolithically thereto, and concerns the formation of a trench isolation structure. Reference will be made hereinafter to this specific application for convenience of illustration.
As is well known, forming an isolation region between two zones of an integrated circuit establishes electrical separation therebetween, and is usually achieved by the interposition of an isolation structure.
One possible isolation structure of a known type is depicted in FIG. 1a, and is described in Patent Application EP 91830151.6, filed on Apr. 17, 1991 by the applicant, and in U.S. Pat. No. 5,432,376, which issued on Jul. 11, 1995 and is based on the EP application.
For simplicity, FIG. 1a shows a circuit including a single low-voltage driver transistor of the npn type and single power transistor, also of the npn type.
This known structure, as described in detail in the above-mentioned patent, uses a diffused zone 4 of the n type, called the junction isolation zone, which separates regions 30 and 31 of the p type to isolate the power stage from the driver circuit.
While being advantageous from several aspects, this solution has a drawback in that it is limiting of the breakdown voltage for the resultant components due to inherent features of the method used, which provides for different concentrations of the various dopants.
Also directed to isolate the power stage from the driver circuit is a second solution, illustrated in FIG. 1b, wherein a dielectric isolation region 14xe2x80x2 is provided instead of the diffused region 4.
While achieving its objective, not even this second solution is devoid of drawbacks.
Most serious of such drawbacks is one inherent to the processing sequence used, on account of the isolation region being defined directly after growing the last epitaxial layer, and in any case before forming either the power or the control components. Due to the materials used to form the dielectric isolation region 14xe2x80x2 having different expansion coefficients, during the high-temperature, typically above 800xc2x0 C., thermal cycles required to form the active regions of the components, the monocrystalline silicon lattice is subjected to considerable stresses which may later be relieved in an unelastic manner by dislocations and other crystal defects likely to impair the circuit performance and functionality.
In general, a temperature below 700 degrees Celsius is often considered a low temperature, and a temperature above 800 degrees Celsius is often considered a high temperature.
This allows some processing steps which entail deposition of materials to be classified as low-temperature steps, whereas the oxidation and diffusion steps would be steps carried out at high temperatures.
However, this is but one example of an isolation scheme known as Deep Trench Isolation (DTI). Comprehensive reviews of known technological approaches are to be found in the references listed here below:
[1] H. Goto and K. Inayoshi, xe2x80x9cTrench Isolation Schemes for Bipolar Devices: Benefits and Limiting Aspects,xe2x80x9d Proceedings of the 17th ESSDERC (Bologna, September 1987), 369-372;
[2] C. Rapisarda, R. Zambrano, F. Baroetto and P. J. Ward, xe2x80x9cReliable Deep Trench Isolation Scheme for High Density, High Performance Bipolar Applications,xe2x80x9d Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 412-413; and
[3] F. Y. Robb et al., xe2x80x9cHigh Voltage Deep Trench Isolation Process Options,xe2x80x9d Isolation and Trench Technology Symposium (Seattle, October 1990), Proceedings of the 178th Electromechanical Society Meeting, 408-409.
References [1] and [2] above deal with the application of the technique to high-performance bipolar devices.
To provide effective isolation, the trench should be extended through the n-type epitaxial layer, approximately 1 micron thick.
The depth attained by the isolation, with this approach, does not exceed 5 microns.
Also known is that, to achieve good planarization, the trench width should not exceed 2 microns, for otherwise, very thick layers of polycrystalline silicon, or polySi, would have to be deposited, resulting in decreased productivity and increased cost of the process.
Some problems connected with the extension of this technique to devices which are to operate at higher voltages are discussed in Reference [3] above.
It is emphasized there, for example, that the trench depth should be increased, because the epitaxial layers to be etched are thicker, being on the order of 15 to 25 microns thick; on the other hand, trenches with aspect ratii (ratio of trench depth to width) higher than 10 are difficult to make.
One object of the present invention is to provide a method of making a structure for isolating two zones of an integrated circuit, which can overcome the aforementioned limitations and/or drawbacks of prior art methods.
According to principles of the invention, the object is achieved by a process for forming, on a semiconductor substrate, a dielectric isolation structure between two zones of an integrated circuit where active regions of electronic components have been previously defined, which process is as outlined above and characterized in that it comprises the following steps of:
defining the isolation zone in the silicon oxide;
selectively etching the silicon;
growing thermal oxide over the interior surfaces of the isolation structure;
depositing conformingly; and
oxidizing the deposited dielectric.
In this way, a dielectric isolation structure is obtained which can also be applied, in quite a straightforward manner, to devices intended for operation at voltages in excess of a few tens of volts.
More particularly, the invention provides for the isolation structure to be formed after the formation of the active zones of the components.
Advantageously, this sequential processing scheme allows the stresses built into the silicon, on account of the materials which enter the making of the isolation by high-temperature processes having different coefficients of thermal expansion, to be minimized.
Additional advantages come from the possibility of using, for the purpose of planarization, different materials for the dielectric ranging from polycrystalline silicon to deposited oxide layers and perhaps organic materials.
All this by virtue of the active zones of the components having been formed earlier, and the only steps left to complete the device being the definition of the contact areas and the steps of metallization and passivation.
It should be further noted that the isolation forming technique of this invention affords high productivity.
In fact, from information reported in Reference [3] above, it can be appreciated that productivity is a variable of the utmost importance.
With the method of this invention, productivity can be kept high at uniquely reduced costs.
Table 1 of Reference [3] can be altered by the addition of the following column to encompass information about our own solution, namely:
That is, wet etch using KOH (potassium hydroxide), an etch rate of one micron per minute, and an hourly capacity of more than one hundred slices.
As can be gathered from Table I, the method of this invention allows isolation regions to be formed to a depth of upwards of 25 microns.
This depth value is often essential to the operation of circuits which contain one or more power transistors and a driver circuit operated at higher voltages than a few tens of volts.